Schottky diodes are employed as rectifiers in numerous power and small signal applications where the forward conduction or switching characteristics of the diode are important. Conventional silicon PN junction diodes have a number of disadvantages, including: (i) a large voltage drop of approximately 700 mV or higher (depending on the level of operating current) when the diode is in its forward conducting state, and (ii) the diode's characteristic of storing a large number of minority carriers when it is in the forward conducting condition, which slows the diode's turn off time and leads to numerous problems relating to diode reverse recovery such as increased power loss, heating, noise and reduced circuit efficiencies.
FIGS. 1a and 1b illustrate the basic reverse recovery problem in conventional silicon PN diodes. FIG. 1a illustrates a common circuit configuration leading to forced diode "reverse" recovery losses, while FIG. 1b describes the voltage and current waveforms which occur during switching operation. During interval .DELTA.t.sub.1 the diode D1 is forward biased to some predetermined current density and forward voltage drop. During interval .DELTA.t.sub.2 some device in series with the diode (such as a MOSFET M1) diverts the current from the current source I1 and causes the current through the junction of diode D1 to decrease at a predetermined slew rate dI/dt. Eventually, in interval .DELTA.t.sub.3 the polarity of the current in diode D1 reverses because its cathode has become more positive than its anode. Since the charge that was stored in diode D1 has not fully been removed, however, diode D1 continues to conduct (in a reverse direction) even though it is reverse-biased. Eventually, the stored charge will be removed (either by recombination or diffusion) and diode D1 will "recover", i.e. stop conducting. The term "reverse recovery" refers to this temporary operating condition wherein current is flowing in a device biased into an reverse polarity.
At the onset of interval .DELTA.t.sub.4, magnitude of the reverse current through diode D1 reaches a peak and begins to decline. At the same time, the reverse voltage across diode D1 begins to rise sharply. The simultaneous presence of substantial voltage and conduction current in diode D1 leads to a power loss and undesirable heating in the diode itself. In a actual application heat generated in the diode is lost power no longer available to do work in the system, and a decrease in efficiency results. The rapid change in voltage likewise produces electrical noise which can be coupled into other parts of the circuit or system. Finally, during interval .DELTA.t.sub.5, as a result of stray inductance the voltage across diode D1 overshoots the supply voltage V.sub.CC. This can lead to oscillations, noise, further power loss or even avalanche breakdown.
In an actual application, the current source I1 may be an inductor as long as the switching frequency is fast relative to the natural R/L time constant of the system. Such a configuration occurs, for example, any time a push-pull driver stage drives an inductor in a switch-mode technique such as a PWM (pulse width modulated) motor driver or switch mode power supply (e.g. in a DC/DC converter).
FIG. 2 illustrates the benefits obtained by reducing the quantity of charge stored in a diode. Both the magnitude of peak reverse recovery current (I.sub.peak) and the duration of the reverse recovery period (t.sub.rec) are reduced in the "low charge" diode. In practice, fast recovery times are achieved in high voltage PIN diodes by reducing minority carrier lifetime through irradiation or platinum doping and in lower voltage applications (below 100V) using a metal-to-silicon Schottky barrier diode instead of a PN junction. At low voltages, the Schottky diode is preferred to the PN junction diode because of its lower forward voltage drop. FIGS. 3a and 3b illustrate the I-V characteristics on both linear and semi-logarithmic graphs. The current I is normalized by area and is represented as the variable J having units of amps/cm.sup.2. FIGS. 3c and 3d illustrate cross-sections of a PIN diode and a Schottky diode, respectively, having the above-mentioned electrical characteristics. The Schottky diode tends to offer a faster reverse recovery time than the PN junction diode, even when lifetime reduction techniques are employed.
The major disadvantage of the Schottky diode is its relatively high offstate leakage current, which is typically orders of magnitude higher than the leakage current of a PN junction diode. Moreover, the leakage current in a Schottky diode is strongly dependent on voltage, as a consequence of reverse-voltage-induced barrier-lowering at the rectifying metal-semiconductor interface (sometimes referred to as the "Schottky interface"). Unfortunately, using a different Schottky barrier metal to adjust the barrier height and thereby reduce current leakage increases the on-state forward voltage drop across the diode, resulting in a difficult tradeoff between on-state and off-state characteristics. The well known equation ##EQU1## where the work function as given by ##EQU2## highlights the tradeoff since the work function is a function of the reverse-voltage Vr. In this equation, q is the charge of an electron (1.times.10.sup.-19 coulombs), N.sub.D is the net doping, V.sub.bi is the built-in potential of the metal/semiconductor interface, V.sub.r is the applied reverse bias, .di-elect cons..sub.s is the permittivity of the semiconductor.
Recently attempts have been made to circumvent this tradeoff by employing a new structure of Schottky diode having a trenched gate. The trench-gated Schottky barrier diode, described in U.S. Pat. No. 5,365,102 to Baliga et al., is shown in cross-section in FIG. 4. Diode 40 is formed in an N+ substrate 42 on which an N-epitaxial layer 44 is deposited. Trenches 46 are created in the top surface of N-epi layer 44 and are lined with an oxide layer 47 and filled with a Schottky barrier metal 48, which also extends over the surface of N-epi layer 44. Diode 40 uses the trenched gate to electrostatically shield the Schottky interface from barrier lowering. In the presence of a reverse voltage, the MOS structure pinches off, i.e. fully depletes, the regions between the trenches before the barrier lowering has a pronounced effect on leakage.
While the concept of the trench gated Schottky barrier diode reduces the tradeoff between forward and reverse currents, it complicates the device by introducing new failure modes. In particular, each trench gate is an etched silicon region lined with a gate quality oxide and filled with a gate electrode material. The gate oxide is therefore subject to strong electric fields while in its off state.
This is evident from FIG. 5, which shows a cross-sectional view of a trench gated Schottky barrier diode at the onset of avalanche breakdown. The substantially horizontal lines are voltage contours, and the spacing between adjacent voltage contours indicates the strength of the electric field. The shaded regions indicate regions of especially high electric fields which are generally located in the vicinity of the trench. These strong electric fields can damage or rupture the gate oxide, particularly during switching transients where inductive loads may drive the device into breakdown. The vertical lines on the left side of the figure represent current flow in avalanche emanating from the bottom of the lefthand trench. To avoid undue complexity the current flows from the other trenches are not shown.
In avalanche breakdown, the generated carriers gain high energies accelerated by the high local electric fields. Such carriers are known as "hot" because their kinetic energy is high compared to their surroundings. The generation rate G (in units of hot carrier pairs generated per cm.sup.3 per second) is an indirect indicator of the energy of the carriers. The shaded portions of FIG. 6 illustrate the regions where G is the highest, and it is evident that this condition occurs near the trench corners. Near an interface a hot carrier may surmount the interface barrier (here a silicon:silicon-dioxide barrier) and become trapped in the dielectric or the interface, altering the charge balance and redistributing the electric field contours. Repeated charge injection subsequently leads to gate oxide wearout and permanent damage to the device. FIG. 6 includes the equipotential and current flow lines that are shown in FIG. 5.
Another form of reliability risk to the trench gate occurs during a voltage transient. The silicon/gate oxide/gate electrode combination acts as an MOS capacitor. Unless a source of carriers is present in a MOS capacitor, a voltage transient resulting in depletion of the silicon can produce a depletion region which extends wider than the equilibrium value ##EQU3## where V.sub.r is the bias across the capacitor, .di-elect cons..sub.s is the permittivity of silicon (equal to 3.9(8.854.times.10.sup.-14 F/cm.sup.2), q is the unit charge of an electron (1.6.times.10.sup.-19 coulombs), and N.sub.D is the doping level of the silicon. The Fermi potential also reflects the doping by the relation ##EQU4## where n.sub.i is the intrinsic carrier concentration (around 1.4.times.10.sup.10 cm.sup.-3 for silicon), and k is the Boltzmann constant.
During the transient, carriers needed to form the inversion layer must be generated thermally within the space charge region. In hyper-pure long lifetime semiconductor material, this time constant can be much longer than the time of the voltage transient. Without the inversion layer, and in order to maintain charge neutrality, the depletion region must continue to expand till the charge-capacitance relationship is satisfied. Such a capacitor is said to be in "deep depletion", the same principle by which CCDs (charge coupled devices) operate. At its full extent, the depletion region in the silicon can go into avalanche temporarily. Since the peak field is at the interface, the avalanche will be located at the worst possible location-against the gate oxide. The resulting avalanche is known as a deep depletion induced avalanche. While the charge injection into the gate oxide is temporary, its effect on the life of the gate oxide is cumulative and eventually can lead to failure.
Bulucea et al., in an article entitled "Field Distribution and Avalanche Breakdown of Trench MOS Capacitors Operated in Deep Diffusion", IEEE Transactions On Electron Devices, Vol. 36, No. 11 (November 1989), analyzed the phenomenon of deep depletion transient avalanche in planar and later in trench shaped MOS capacitors and showed the effect includes both gate oxide thickness and background doping effects. FIG. 7a, taken from the Bulucea et al. article, shows the deep-depletion breakdown voltage V.sub.B(WIDE) of a wide-trench MOS capacitor operated in deep depletion versus the background impurity concentration N.sub.B and the gate oxide thickness t.sub.ox. FIG. 7b, also taken from the Bulucea et al. article, shows the deep-depletion breakdown voltage V.sub.B of a narrow-trench MOS capacitor, normalized to V.sub.B(WIDE), versus the trench half-width w/2 and background impurity concentration N.sub.B. Since the field plate effect is more pronounced for thinner gate oxides, the onset of breakdown varies in proportion to the gate oxide--the thinner the oxide the lower the breakdown. The breakdown dependence on background doping exhibits a more complex U-shaped dependence. The breakdown minimum of any curve represents the worst case (i.e. lowest breakdown) concentration where the electric fields are high but the mean free path of the carriers is relatively long. Specifically, in avalanche carriers collide with atoms within the crystal, giving up their kinetic energy and occasionally breaking the crystal bond of the atom with which they collide. If the speed of the carriers is high because they have traveled sufficiently far to accelerate to an energy capable of breaking bonds, then more electron hole pairs are generated and the critical field of breakdown drops.
If the dopant concentration is increased to a high enough value, collisions between the carriers and the ionized dopant atoms become so likely that only a few carriers ever accelerate to high speeds. Consequently fewer bonds are broken, fewer electron hole pairs are generated and the avalanche process starves for carriers, thereby increasing the critical electric field and breakdown voltage despite higher electric fields.
In summary, increasing the impurity dopant concentrations in silicon raises the strength of the electric field but lowers carrier mobility (mean free path), leading to a minimum value for avalanche in a deeply depleted MOS capacitor. For concentrations below this minimum avalanche breakdown value, a decrease in doping leads to an improvement in breakdown because the electric fields are reduced. For concentrations above the minimum avalanche breakdown value, the adverse effect of the field increase is more than compensated for by the reduced mean free path of the carriers. The ionization coefficient, a figure of merit of how easily the excited carriers form more carriers, is thereby reduced, and the breakdown increases. Since the value of fields in the silicon are determined by the capacitive "voltage divider" represented by the MOS oxide capacitor and the silicon depletion region, a thicker gate oxide demands that more voltage be applied to reach the avalanche condition, and the value of the transient breakdown increases. Some values of the maximum concentration which meets a given breakdown (from FIG. 7a) are included in the table below for convenience. Concentrations lower than 10.sup.16 are probably not useful because of the series resistance of the diode.
__________________________________________________________________________ Gate ox Minimum MOS Transient Breakdown thickness 10V 20V 40V 60V 100V 200V __________________________________________________________________________ 100 .ANG. 8 .multidot. 10.sup.17 3 .multidot. 10.sup.16 4 .multidot. 10.sup.15 1.8 .multidot. 10.sup.15 5.5 .multidot. 10.sup.14 1.5 .multidot. 10.sup.14 200 .ANG. 5 .multidot. 10.sup.16 4.8 .multidot. 10.sup.15 2 .multidot. 10.sup.15 6.5 .multidot. 10.sup.14 1.8 .multidot. 10.sup.14 500 .ANG. 1 .multidot. 10.sup.16 3.3 .multidot. 10.sup.15 1 .multidot. 10.sup.15 2.3 .multidot. 10.sup.14 1000 .ANG. 1 .multidot. 10.sup.18 2.5 .multidot. 10.sup.16 5.2 .multidot. 10.sup.15 1.2 .multidot. 10.sup.15 3 .multidot. 10.sup.14 2000 .ANG. 1 .multidot. 10.sup.18 2 .multidot. 10.sup.16 2 .multidot. 10.sup.15 4 .multidot. 10.sup.14 5000 .ANG. 1 .multidot. 10.sup.18 7 .multidot. 10.sup.14 10000 .ANG. 1 .multidot. 10.sup.18 1 .multidot. 10.sup.18 2 .multidot. 10.sup.15 __________________________________________________________________________
From this table we can see that unless a method is employed to prevent transient deep depletion avalanche in the trench Schottky, the device is limited to operation with voltages below 100V. If thin gate oxides (e.g. 1000 .ANG. or below), the prior art device is practically limited to operation only at 40V.
While U.S. Pat. No. 5,072,266 to Bulucea addresses the issue of protecting the gate of a trench-gated power MOSFET, the above-mentioned U.S. Pat. No. 5,365,102 does not discuss hot carrier effects or their implications on the reliability of the trench. In regards to sustained avalanche of the trench Schottky diode, U.S. Pat. No. 5,365,102 also fails to address or discuss the energy absorbing capability of the trench-gated Schottky diode. In the circuit shown in FIG. 8, for example, a diode 80 must clamp the positive voltage excursion caused by interrupting the current in the inductive load 82 or parasitic inductance. When the current is interrupted (at time t.sub.1), the entire energy stored in inductive load 82 (0.5LI.sup.2) will be dumped into diode 80. FIG. 8 shows the behavior of the voltage and current when this happens. The duration of this event depends on the parasitic series resistance of the circuit. The high avalanche surge current, in addition to generating hot carriers which may damage the gate oxide lining the trench can also affect the metal-silicon Schottky interface, particularly considering that a trench-gated Schottky diode is normally designed to operate at higher current densities than a conventional Schottky diode. Electromigration of the Schottky barrier metal and localized heating during large avalanche surge currents can burn the device out in hundreds of milliseconds.
Another problem during avalanche occurs in low voltage diodes where the doping is large. Such is the case if the trench gate runs into an N+ layer, for example, as shown in the cross-sectional view of FIG. 9. If the doping of the N+ layer 90 is sufficiently high that there is only a small voltage drop across the silicon of the trench MOS capacitor, then the gate oxide 92, which sees almost the entire voltage across the device, may rupture instantly. In other words, there is practically no energy absorbing capability whatsoever before the onset of device damage.
Yilmaz et al. suggested in U.S. Pat. No. 5,168,331 modifying the dopant concentration at the bottom of the trench using a counterdoping well implant into the trench to minimize impact ionization in its vicinity. This method, while it does reduce the impact ionization some at the onset of breakdown, does not improve the overall energy absorbing capability of the diode and in deep avalanche (whether transient or steady state) cannot protect the trench gate from hot carriers traveling across the counterdoped region to damage the gate oxide. Making the counterdoped region wider will also increase the diode's series resistance, thereby mitigating one of the beneficial aspects of the trench-gated Schottky diode.
What is needed is a method to protect a trench-gated Schottky diode damage arising from avalanche breakdown or hot carrier generation and to categorically prevent the electric field across the gate oxide from reaching dangerous levels.